The present invention relates to a content addressable memory (CAM) using semiconductor elements, and particularly to a content addressable memory capable of higher speed operation than conventional.
Generally, with the progress of high integration of a semiconductor memory and a great increase in capacity thereof, a high-speed operation of the semiconductor memory becomes difficult. This is because as one cause thereof, a signal propagation delay occurs due to an increase in wiring capacitance with an increase in the number of memory cells coupled to each wiring.
A technology disclosed in Japanese Unexamined Patent Publication No. Hei 10 (1998)-255477 (Patent document 1) aims to eliminate a propagation delay in the drive control signal outputted from a word line drive circuit. The word line drive circuit of this document includes a signal generation unit, a first driver circuit, a second driver circuit and a speedup driver circuit. The signal generation unit generates a drive signal at a predetermined timing. The first driver circuit drives one end side of a first wiring to which a plurality of controlled circuits are coupled, in response to the drive signal. The second driver circuit drives one end side of a second wiring smaller in drive load than the first wiring in response to the drive signal. The speedup driver circuit has an input coupled to the other end side of the second wiring and the other end side of the first wiring, and an output terminal for driving the other end side of the first wiring when the level of the other end side of the first wiring and the level of the other end side of the second wiring are not coincident with each other.
Japanese Unexamined Patent Publication No. 2001-357675 (Patent document 2) discloses a technology for making access time at reading faster. A semiconductor memory device described in this document includes memory cells arranged in a column direction, a pair of digit lines coupled to each memory cell, and word lines laid so as to intersect with the digit lines respectively and for selecting the respective memory cells. Further, the semiconductor memory device includes a sense amplifier disposed at one ends of the digit lines, a near-end side precharge circuit disposed in the vicinity of the sense amplifier with respect to the digit lines, and a far-end side precharge circuit disposed at the ends of the digit lines on the side opposite to the sense amplifier. Such a semiconductor memory device has a feature that the time at which a precharge operation of the far-end side precharge circuit at a read operation is completed is simultaneous with or earlier than that of the near-end side precharge circuit. Preferably, a signal for selecting each word line lying on the side close to the far-end side precharge circuit at the read operation rises earlier than a signal for selecting each word line lying on the side close to the near-end side precharge circuit.